A test system for examining the characteristics of an Integrated Services Digital Networks (ISDN), an A/D converter and the like performs digital calculations such as Fourier transformation, Fourier inverse-transformation and other filtering functions. In order to increase the processing speed, a digital signal processor, hereinafter referred to as "DSP", has been used.
FIG. 1 schematically illustrates an embodiment of a multi-processor type signal processing system which comprises three DSP units 30A, 30B, 30C and a CPU 1 for controlling these units. The units 30A, 30B, and 30C are respectively equipped with DSPs 31A, 31B, and 31C, memories 32A, 32B, and 32C and external I/O devices 33A, 33B and 33C. During operation, in the unit 30A, for example, I/O data is accessed from the I/O device 33A and is then sent to the DSP 31A and subjected to processing such as Fourier transformation. The processed data is then transferred to the unit 30B through a peripheral I/O interface (not shown) and subjected to further processing such as filtering in the DSP 31B. The processed data is then transferred to the unit 30C through a peripheral I/O interface (also not shown). The processed data is then subjected to a further processing such as Fourier inverse-transformation by the DSP 31C, and the processed result is transferred to external I/O device 33C for output.
In addition to executing a high-speed processing program, the DSP generally has other functions for executing various processes. These tasks include access to the external I/O devices for receiving data from various output devices such as an A/D converter, a D/A converter, various types of peripheral I/O interfaces, etc., and for transferring the computed data to other external I/O devices. The following methods have been known for transferring data during reception and transmission to/from external I/O devices: (1) the data receiving and transmitting operations are carried out through an interrupt to the computer program of the DSP; and (2) with no interrupt, the data is temporarily stored in an external register file and then the data reception and transmission are successively carried out.
FIG. 2 is a schematic circuit diagram of an embodiment of a conventional digital signal processing system utilizing the method (1). In FIG. 2, a DSP 2 controls an access to a memory 5, an A/D converter 3, and a peripheral I/O interface 4 through common busses such as data bus 6 and address bus 7. A decoder 8 is further provided in the address bus 7 to output an enable signal to the A/D converter 3 and the peripheral I/O interface 4. In addition, through the common system bus, the CPU 1 performs various processing including controlling the DSP 2, loading down the DSP program to the memory 5, and so on.
The DSP 2 runs a DSP program in the memory 5 which serves as a real-time monitor. Instructions for the DSP 2 are programmed in the real-time monitor in such a manner that a series of signal processing blocks are constructed as a processing task. These programs are executed under the management of a scheduler. However, the I/O processing is carried out as a different task from the above task. The I/O processing is commenced by an interrupt through a data enable signal of the A/D converter 3 and serves to temporarily transfer input data from the A/D converter 3 to a buffer 51 indicated as an area in the memory 5 in FIG. 2. A semaphore serving as a real-time monitor also may be set up in the buffer 51. Then, when data to be processed exists in the buffer 51, the DSP 2 synchronizes with the data based upon the semaphore value and transfers the data to a signal processing task which is waiting for the data.
However, since this method requires interrupt processing for receiving input data from A/D converter 3, it usually increases the processor load in the DSP 2. For example, the data receiving operation of the DSP 2 from the A/D converter 3 is executed through an interrupt and makes it impossible for the DSP 2 to carry out other processing such as high-speed computing operations during the execution of the above processing. The processing capability of the DSP 2 is thereby greatly restricted.
In addition, if it takes longer for the DSP 2 to process I/O data than the I/O period of the I/O device, some data may be left behind after the processing. Accordingly, the data I/O period of the I/O device is restricted by the DSP 2 processing speed. For example, the sampling rate of the A/D converter 3 such as shown in FIG. 2 or a generation rate of the D/A converter is restricted by the processing speed of the DSP 2. Therefore, this method has a disadvantage that the I/O device speed cannot be increased beyond the speed of the DSP 2.
In view of the above restriction, when implementing the method (2) using a circuit as shown in FIG. 3, the I/O processing is not carried out as a different task but is carried out with an instruction contained in a signal processing task. According to this method, an external register file 9 is provided between the A/D converter 3 and the DSP 2 and performs the synchronization of the data without a real-time monitor. That is, this method does not use an interrupt to communicate with the monitor program. Instead, the register file 9 performs an I/O data operation in response to a read/write command in a task for a series of signal processing tasks until it reaches the I/O limitation of the register file 9. Such an I/O limitation includes the operation period of the I/O device.
In actual operation, the DSP 2 checks the contents of the register file 9 to ascertain whether data exists in the register file 9. If there is no data in the register file 9, the DSP 2 is placed in a waiting state so that it is not required to carry out another process such as checking the content of the semaphore in accordance with method (1). Since the DSP 2 accesses the I/O devices through the register file 9, the DSP 2 requires no interrupt processing. Thus, the burden imposed on the DSP 2 in association with the data I/O processing can be alleviated.
However, this method has a disadvantage that during this waiting state, the DSP 2 still cannot carry out any other processing, which results in processing overhead. Thus, the total processing efficiency of the system is reduced due to processing overhead. This method has a further disadvantage that the register file 9 is comprised of expensive hardware which increases the total cost of the system. Moreover, many register files are sometimes required for one system so that this method results in a large increase in the total manufacturing cost for the system. Further, when the data input and output period exceeds the processing period of the DSP 2, the input data to the register file 9 is overflowed, and thus, some data may be lost.